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a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700www.analog.com fax: 781/326-8703 ? analog devices, inc., 2002 ad6645 14-bit, 80 msps a/d converter rev. 0 features 80 msps guaranteed sample rate snr = 75 db, f in 15 mhz @ 80 msps snr = 72 db, f in 200 mhz @ 80 msps sfdr = 89 dbc, f in 70 mhz @ 80 msps 100 db multitone sfdr if sampling to 200 mhz sampling jitter 0.1 ps 1.5 w power dissipation differential analog inputs pin-compatible to ad6644 twos complement digital output format 3.3 v cmos-compatible dataready for output latching applications multichannel, multimode receivers base station infrastructure amps, is-136, cdma, gsm, wcdma single channel digital receivers antenna array processing communications instrumentation radar, infrared imaging instrumentation product description the ad6645 is a high-speed, high-performance, monolithic 14-bit analog-to-digital converter. all necessary functions, including track-and-hold (t/h) and reference, are included on the chip to provide a complete conversion solution. the ad6645 provides cmos-compatible digital outputs. it is the fourth generation in a wideband adc family, preceded by the ad9042 (12-bit, 41 msps), the ad6640 (12-bit, 65 msps, if sampling), and the ad6644 (14-bit, 40 msps/65 msps). designed for multichannel, multimode receivers, the ad6645 is part of analog device s softcell ? transceiver chipset. the ad6645 maintains 100 db multitone, spurious-free dynamic range (sfdr) through the second nyquist band. this break- through performance eases the burden placed on multimode digital receivers (software radios) that are typically limited by the adc. noise performance is exceptional; typical signal-to- noise ratio is 74.5 db through the first nyquist band. the ad6645 is built on analog devices high-speed complemen- tary bipolar process (xfcb) and uses an innovative, multipass circuit architecture. units are available in a thermally enhanced 52- lead powerquad 4 ? (lqfp_ed) specified from C 40 c to +85 c. product highlights 1. if sampling the ad6645 maintains outstanding ac performance up to input frequencies of 200 mhz. suitable for multicarrier 3g wideband cellular if sampling receivers. 2. pin compatibility the adc has the same footprint and pin layout as the ad6644, 14-bit 40 msps/65 msps adc. 3. sfdr performance and oversampling multitone sfdr performance of C 100 dbc can reduce the requirements of high-end rf components and allows the use of receive signal processors such as the ad6620 or ad6624/ ad6624a. functional block diagram 5 a1 th2 a2 th4 adc3 th5 th3 th1 dac1 adc2 dac2 adc1 6 ain ain vref encode encode av cc dv cc gnd dmid ovr dry d13 msb d12 d11 d10 d 9d8d7d6d5d4d3d2d1d0 lsb internal timing 5 digital error correction logic ad6645 2.4v softcell is a trademark of analog devices, inc. powerquad 4 is a registered trademark of amkor technology, inc.
rev. 0 ?2? ad6645 dc specifications AD6645ASQ-80 parameter temp test level min typ max unit resolution 14 bits accuracy no missing codes full ii guaranteed offset error full ii ? 10 +1.2 +10 mv gain error full ii ? 10 0 +10 % fs differential nonlinearity (dnl) full ii ? 1.0 0.25 +1.5 lsb integral nonlinearity (inl) full v 0.5 lsb temperature drift offset error full v 1.5 ppm/ ! c gain error full v 48 ppm/ ! c power supply rejection (psrr) 25 ! cv 1.0 mv/v reference out (vref) 1 full v 2.4 v analog inputs (ain, ain di di w differential input capacitance 25 ! cv 1.5 pf power supply supply voltages av cc full ii 4.75 5.0 5.25 v dv cc full ii 3.0 3.3 3.6 v supply current i av cc (av cc = 5.0 v) full ii 275 320 ma i dv cc (dv cc = 3.3 v) full ii 32 45 ma rise time 2 av cc full iv tbd ms power consumption full ii 1.5 1.75 w notes 1 vref is provided for setting the common-mode offset of a differential amplifier such as the ad8138 when a dc-coupled analog inp ut is required. vref should be buffered if used to drive additional circuit functions. 2 specified for dc supplies with linear rise-time characteristics. the use of dc supplies with linear rise-times of <45 ms is hig hly recommended. specifications subject to change without notice digital specifications AD6645ASQ-80 parameter (conditions) temp test level min typ max unit encode inputs (enc, enc di i di c w differential input capacitance 25 ! cv 2.5 pf logic outputs (d13 ? d0, dry, ovr 2 ) logic compatibility cmos logic ? 1 ? voltage (dv cc = 3.3 v) 3 full ii 2.85 dv cc ? 0.2 v logic ? 0 ? voltage (dv cc = 3.3 v) 3 full ii 0.2 0.5 v output coding two ? s complement dmid full v dv cc /2 v notes 1 all ac specifications tested by driving encode and encode o c c dd cc c oad c a cc d cc in c, t max = +85 c, unless otherwise noted.) (av cc = 5 v, dv cc = 3.3 v; t min = e40 c, t max = +85 c, unless otherwise noted.) especifications
rev. 0 ?3? ad6645 ac specifications 1 AD6645ASQ-80 parameter (conditions) temp test level min typ max unit snr analog input 15.5 mhz 25 encode a icineciicaion ada c c ii c i encode enc i encode enc i enc enc a cc d cc encode encode n c c cc d cc encode encode n c c
rev. 0 ad6645 ?4? switching specifications (continued) AD6645ASQ-80 parameter (conditions) name temp test level min typ max unit encode input parameters 1 encode period 1 @ 80 msps t enc full v 12.5 ns encode pulsewidth high 2 @ 80 msps t ench full v 6.25 ns encode pulsewidth low @ 80 msps t encl full v 6.25 ns encode/dataready encode rising to dataready falling t dr full v 1.0 2.0 3.1 ns encode rising to dataready rising t e_dr full v t ench + t dr ns @ 80 msps (50% duty cycle) full v 7.3 8.3 9.4 ns encode/data (d13:0), ovr enc to data falling low t e_fl full v 2.4 4.7 7.0 ns enc to data rising low t e_rl full v 1.4 3.0 4.7 ns encode to data delay (hold time) 3 t h_e full v 1.4 3.0 4.7 ns encode to data delay (setup time) 4 t s_e full v t enc ? t e_fl ns encode = 80 msps (50% duty cycle) full v 5.3 7.6 10.0 ns dataready (dry 5 )/data, ovr dataready to data delay (hold time) 2 t h_dr full v note 6 ns encode = 80 msps (50% duty cycle) 6.6 7.2 7.9 dataready to data delay (setup time) 2 t s_dr full v note 6 ns encode = 80 msps (50% duty cycle) 2.1 3.6 5.1 aperture delay t a 25 newt h_dr = (t h_dr ?% change(t ench )) newt s_dr = (t s_dr ?% change(t ench )) 3 encode to data delay (hold time) is the absolute minimum propagation delay through the analog-to-digital converter, t e_rl = t h_e . 4 encode to data delay (setup time) is calculated relative to 80 msps (50% duty cycle). to calculate t s_e for a given encode, use the following equation: newt s _ e = t enc ( new ) ? t enc + t s _ e (i.e., for 40 msps: newt s _ e ( typ ) = 25 10 ? 9 ? 15.38 10 ? 9 + 9.8 10 ? 9 = 19.4 10 ? 9 ). 5 dry is an inverted and delayed version of the encode clock. any change in the duty cycle of the clock will correspondingly chan ge the duty cycle of dry. 6 dataready to data delay (t h_dr and t s_dr ) is calculated relative to 80 msps (50% duty cycle) and is dependent on t enc and duty cycle. to calculate t h_dr and t s_dr for a given encode, use the following equations: newt h _ dr = t enc ( new ) /2 ? t ench + t h_ dr (i.e., for 40 msps: newt h _ dr ( typ ) = 12.5 10 ? 9 ? 6.25 10 ? 9 + 7.2 10 ? 9 = 13.45 10 ? 9 newt s_dr = t enc ( new ) /2 ? t ench + t s _ dr (i.e., for 40 msps: newt s _ dr ( typ ) = 12.5 10 ? 9 ? 6.25 10 ? 9 + 3.6 10 ? 9 = 9.85 10 ? 9 specifications subject to change without notice. t s_dr t a ain n n+1 n+2 n+3 n+4 t enc t ench t encl t e_fl t e_rl t e_dr t s_e t h_e t dr t h_dr nn+1n+2n +3 n+4 n n?1 n?2 n?3 enc, enc d13 o d 1 t d a cc d cc 33 encode encode t in c t a c c oad 1
rev. 0 ?5? ad6645 absolute maximum ratings * parameter min max unit electrical av cc voltage 0 7 v dv cc voltage 0 7 v analog input voltage 0 av cc v analog input current 25 ma digital input voltage 0 av cc v digital output current 4 ma environmental operating temperature range (ambient) C C C
rev. 0 ad6645 ?6? pin configuration 52 51 50 49 48 43 42 41 40 47 46 45 44 14 15 16 17 18 19 20 21 22 23 24 25 26 1 2 3 4 5 6 7 8 9 10 11 13 12 pin 1 identifier top view (not to scale) 39 38 37 36 35 34 33 32 31 30 29 28 27 ad6645 av cc gnd av cc gnd av cc gnd gnd av cc gnd c2 gnd av cc dry d13 (msb) d12 d11 d10 d9 d8 d7 dv cc gnd d5 d4 dv cc gnd vref gnd enc enc gnd av cc av cc gnd ain ain gnd d3 d2 d1 d0 (lsb) dmid gnd dv cc ovr dnc av cc gnd av cc gnd c1 d6 dnc = do not connect pin function descriptions pin no. mnemonic function 1, 33, 43 dv cc 3.3 v power supply (digital) output stage only 2, 4, 7, 10, 13, gnd ground 15, 17, 19, 21, 23, 25, 27, 29, 34, 42 3 vref 2.4 v reference. bypass to ground with a 0.1 m f microwave chip capacitor. 5 enc encode input. conversion initiated on rising edge. 6 enc cencdi a cc a ain ai ain caindai c i c i dnc d o oa did odad cc d do C C C C
rev. 0 ?7? ad6645 definitions of specifications analog bandwidth the analog input frequency at which the spectral power of the fundamental frequency (as determined by the fft analysis) is reduced by 3 db. aperture delay the delay between the 50% point of the rising edge of the en code command and the instant at which the analog input is sampled. aperture uncertainty (jitter) the sample-to-sample variation in aperture delay. differential analog input resistance, differential analog input capacitance, and differential analog input impedance the real and complex impedances measured at each analog input port. the resistance is measured statically and the capaci- tance and differential input impedances are measured with a network analyzer. differential analog input voltage range the peak-to-peak differential voltage that must be applied to the converter to generate a full-scale response. peak differential voltage is computed by observing the voltage on a single pin and subtracting the voltage from the other pin, which is 180 degrees out of phase. peak-to-peak differential is computed by rotating the inputs phase 180 degrees and taking the peak measurement again. then the difference is computed between both peak measurements. differential nonlinearity the deviation of any code width from an ideal 1 lsb step. encode pulsewidth/duty cycle pulsewidth high is the minimum amount of time that the encode pulse should be left in logic ? 1 ? state to achieve rated performance; pulsewidth low is the minimum time encode pulse should be left in low state. see timing implica- tions of changing t ench in text. at a given clock rate, these specs define an acceptable encode duty cycle. full-scale input power expressed in dbm. computed using the following equation: power v z full scale full scale rms input = ? ? 10 0 001 2 log || . harmonic distortion, 2 nd the ratio of the rms signal amplitude to the rms value of the second harmonic component, reported in dbc. harmonic distortion, 3 rd the ratio of the rms signal amplitude to the rms value of the third harmonic component, reported in dbc. integral nonlinearity the deviation of the transfer function from a reference line measured in fractions of 1 lsb using a ? best straight line ? determ ined by a least square curve fit. minimum conversion rate the encode rate at which the snr of the lowest analog signal frequency drops by no more than 3 db below the guaranteed limit. maximum conversion rate the encode rate at which parametric testing is performed. noise (for any range within the adc) vz noise fs snr signal dbm dbc dbfs = - ? ? ? || . ? 0 001 10 10 where z is the input impedance, fs is the full scale of the device for the frequency in question; snr is the value for the particular input level; and signal is the signal level within the adc re ported in db below full scale. this value includes both thermal and quantization noise. output propagation delay the delay between a differential crossing of encode and encode and the time when all output data bits are within valid logic levels. power supply rejection ratio the ratio of a change in input offset voltage to a change in power supply voltage. power supply rise time the time from when the dc supply is initiated, until the supply output reaches the minimum specified operating voltage for the adc. the dc level is measured at supply pin(s) of the adc. signal-to-noise-and-distortion (sinad) the ratio of the rms signal amplitude (set 1 db below full scale) to the rms value of the sum of all other spectral components, including harmonics but excluding dc. signal-to-noise ratio (without harmonics) the ratio of the rms signal amplitude (set at 1 db below full scale) to the rms value of the sum of all other spectral compo- nents, excluding the first five harmonics and dc. spurious-free dynamic range (sfdr) the ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. the peak spurious component may or may not be a harmonic. may be reported in dbc (i.e., degrades as signal level is lowered) or dbfs (always related back to converter full scale). two tone intermodulation distortion rejection the ratio of the rms value of either input tone to the rms value of the worst third order intermodulation product; reported in dbc. two tone sfdr the ratio of the rms value of either input tone to the rms value of the peak spurious component. the peak spurious component may or may not be an imd product. may be reported in dbc (i.e., degrades as signal level is lowered) or in dbfs (always related back to converter full scale). worst other spur the ratio of the rms signal amplitude to the rms value of the worst spurious component (excluding the second and third harmonic) reported in dbc.
rev. 0 ad6645 ?8? equivalent circuits buf t/h buf buf t/h v ch av cc 500 v cl ain v ch av cc v cl ain 500 v ref figure 2. analog input stage loads loads 10k 10k 10k 10k enc enc av cc av cc av cc av cc figure 3. encode inputs av cc current mirror v ref av cc av cc c1, c2 figure 4. compensation pin, c1 or c2 current mirror current mirror v ref d0? d13 , ovr, dry dv cc dv cc figure 5. digital output stage av cc av cc v ref 100 a 2.4v figure 6. 2.4 v reference 10k dmid 10k dv cc figure 7. dmid reference
rev. 0 ?9? ad6645 frequency ? mhz ?130 0510 15 20 25 30 35 40 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 encode = 80msps ain = 2.2mhz @ ?1dbfs snr = 75.0db sfdr = 93.0dbc dbfs 2 6 5 4 3 tpc 1. single tone @ 2.2 mhz frequency ? mhz ?130 0510 15 20 25 30 35 40 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 dbfs 2 6 5 4 3 encode = 80msps ain = 15.5mhz @ ?1dbfs snr = 75.0db sfdr = 93.0dbc tpc 2. single tone @ 15.5 mhz frequency ? mhz ?130 051015 20 25 30 35 40 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 encode = 80msps ain = 29.5mhz @ ?1dbfs snr = 74.5db sfdr = 93.0dbc dbfs 2 6 5 4 3 tpc 3. single tone @ 29.5 mhz t ypical performance characteristicse frequency ? mhz ?130 0510 15 20 25 30 35 40 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 encode = 80msps ain = 69.1mhz @ ?1dbfs snr = 73.5db sfdr = 89.0dbc dbfs 2 6 5 4 3 tpc 4. single tone @ 69.1 mhz frequency ? mhz ?130 0510 15 20 25 30 35 40 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 dbfs 2 6 5 4 3 encode = 80msps ain = 150mhz @ ?1dbfs snr = 73.0db sfdr = 70.0dbc tpc 5. single tone @ 150 mhz frequency ? mhz ?130 051015 20 25 30 35 40 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 dbfs 2 6 5 4 3 encode = 80msps ain = 200mhz @ ?1dbfs snr = 72.0db sfdr = 64.0dbc tpc 6. single tone @ 200 mhz
rev. 0 ad6645 ?10? frequency ? mhz snr ? db 0102 03040506070 encode = 80msps @ ain = ?1dbfs temp = ?40 c, +25 c, +85 c 72.0 72.5 73.0 73.5 74.0 74.5 75.0 75.5 t = +25 c t = +85 c t = ?40 c tpc 7. noise vs. analog frequency analog input frequency ? mhz worst case harmonic ? dbc 010203 040506070 encode = 80msps @ ain = ?1dbfs temp = ?40 c, +25 c, +85 c 80 82 84 86 88 90 92 94 t = +25 c t = ?40 c, +85 c tpc 8. harmonics vs. analog frequency analog frequency ? mhz snr ? db 020 80 40 100 60 encode = 80msps @ ain = ?1dbfs temp = 25 c 70 71 72 73 74 75 76 120 140 160 180 200 tpc 9. noise vs. analog frequency (if) analog frequency ? mhz harmonics ? dbc 020 80 40 100 60 encode = 80msps @ ain = ?1dbfs temp = 25 c 60 65 120 140 160 180 200 70 80 90 100 75 85 95 worst other spur harmonics (2nd, 3rd) tpc 10. harmonics vs. analog frequency (if) analog input power level ? dbfs worst case spurious ? dbfs and dbc 0 ?90 10 20 30 40 50 60 70 80 90 100 110 ?80 ?70 ?60 ?50 ?40 ?30 ?20 encode = 80msps ain = 30.5mhz dbc sfdr = 90db reference line 120 dbfs ?10 0 tpc 11. single tone sfdr @ 30.5 mhz analog input power level ? dbfs worst case spurious ? dbfs and dbc 0 ?90 10 20 30 40 50 60 70 80 90 100 110 ?80 ?70 ?60 ?50 ?40 ?30 ?20 encode = 80msps ain = 69.1mhz dbc sfdr = 90db reference line 120 dbfs ?10 0 tpc 12. single tone sfdr @ 69.1 mhz
rev. 0 ?11? ad6645 encode = 80msps ain = 30.5mhz, 31.5mhz (?7dbfs) no dither frequency ? mhz ?130 051015 20 25 30 35 40 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 dbfs 2 f 1 + f 2 f 1 + f 2 f 2 ? f 1 2 f 2 + f 1 2 f 1 ? f 2 2 f 2 ? f 1 tpc 13. two tones @ 30.5 mhz and 31.5 mhz input power level ? f1 = f2 dbfs worst case spurious ? dbfs and dbc 0 ?77 10 20 30 40 50 60 70 80 90 100 110 ?67 ?57 ?47 ?37 ?27 ?17 ?7 encode = 80msps f1 = 30.5mhz f2 = 31.5mhz dbc dbfs sfdr = 90db reference line tpc 14. two tone sfdr @ 30.5 mhz and 31.5 mhz encode frequency ? mhz snr, worst case spurious ? db and dbc 15 65 70 80 90 30 45 60 75 90 105 worst spur @ ain = 2.2mhz snr @ ain = 2.2mhz 75 85 95 100 tpc 15. snr, worst spurious vs. encode @ 2.2 mhz 2 f 2 ? f 1 encode = 80msps ain = 55.25mhz, 56.25mhz (?7dbfs) no dither frequency ? mhz ?130 0510 15 20 25 30 35 40 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 dbfs 2 f 1 + f 2 f 1 + f 2 f 2 ? f 1 2 f 2 + f 1 2 f 1 ? f 2 tpc 16. two tone sfdr @ 55.25 mhz and 56.25 mhz ?77 ?67 ?57 ?47 ?37 ?27 ?17 ?7 input power level ? f1 = f2 dbfs worst case spurious ? dbfs and dbc 0 10 20 30 40 50 60 70 80 90 100 110 encode = 80msps f1 = 55.25mhz f2 = 56.25mhz dbc dbfs sfdr = 90db reference line tpc 17. two tone sfdr @ 55.25 mhz and 56.25 mhz encode frequency ? mhz snr, worst case spurious ? db and dbc 15 65 70 80 90 30 45 60 75 90 105 worst spur @ ain = 69.1mhz snr @ ain = 69.1mhz 75 85 95 tpc 18. snr, worst spurious vs. encode @ 69.1 mhz
rev. 0 ad6645 ?12? frequency ? mhz 0 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 5101 52025303540 5 3 2 6 4 dbfs encode = 80.0msps ain = 30.5mhz @ ?29.5 dbfs no dither tpc 19. 1 m fft without dither analog input level 90 0 10 20 30 40 50 60 70 80 90 100 110 80 70 60 50 40 30 20 10 0 dbfs encode = 80.0msps ain = 30.5mhz no dither sfdr = 90 db reference line worst-case spurious dbc tpc 20. sfdr without dither frequency ? mhz ?130 0510 15 20 25 30 35 40 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 dbfs 2 6 5 4 3 encode = 76.8msps ain = 69.1mhz @ ?1dbfs snr = 73.5db sfdr = 89.0dbc tpc 21. single tone 69.1 mhz: encode = 76.8 msps frequency ? mhz ?130 051015 20 25 30 35 40 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 5 3 2 6 4 dbfs encode = 80.0msps ain = 30.5mhz @ ?29.5dbfs with dither @ ?19.2 dbm tpc 22. 1 m fft with dither analog input level ?90 0 10 20 30 40 50 60 70 80 90 100 110 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 dbfs encode = 80.0msps ain = 30.5mhz with dither @ ?19.2 dbm sfdr = 90 db reference line sfdr = 100 db reference line worst-case spurious dbc tpc 23. sfdr with dither frequency ? mhz ?130 0510 15 20 25 30 35 40 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 dbfs 2 6 5 4 3 encode = 76.8msps ain = wcdma @ 69.1mhz tpc 24. wcdma tone 69.1 mhz: encode = 76.8 msps
rev. 0 ?13? ad6645 frequency ? mhz ?130 051015 20 25 30 35 40 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 dbfs encode = 76.8msps ain = 2wcdma @ 59.6mhz tpc 25. 2 wcdma carriers @ a in = 59.6 mhz: encode = 76.8 msps frequency ? mhz 02 .5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 encode = 61.44msps ain = 4wcdma @ 46.08mhz dbfs tpc 26. 4 wcdma carriers @ a in = 46.08 mhz: encode = 61.44 msps 6 5 4 2 3 frequency ? mhz ?130 0 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 5101 52025303540 encode = 76.8msps ain = wcdma @ 140mhz dbfs tpc 27. wcdma tone 140 mhz: encode = 76.8 msps ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 2 3 6 4 5 encode = 61.44msps ain = wcdma @ 190mhz dbfs frequency ? mhz 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0 tpc 28. wcdma tone 190 mhz: encode = 61.44 msps
rev. 0 ad6645 ?14? theory of operation the ad6645 analog-to-digital converter (adc) employs a three stage subrange architecture. this design approach achieves the required accuracy and speed while maintaining low power and small die size. as shown in the functional block diagram, the ad6645 has complementary analog input pins, ain and ain . each analog input is centered at 2.4 v and should swing 0.55 v around this reference (see figure 2). since ain and ain are 180 de grees out of phase, the differential analog input signal is 2.2 v peak- to-peak. both analog inputs are buffered prior to the first track-and-hold, th1. the high state of the encode pulse places th1 in hold mode. the held value of th1 is applied to the input of a 5-bit coarse adc1. the digital output of adc1 drives a 5-bit digital- to-analog converter, dac1. dac1 requires 14 bits of precision, which is achieved through laser trimming. the output of dac1 is subtracted from the delayed analog signal at the input of th3 to generate a first residue signal. th2 provides an analog pipe- line delay to compensate for the digital delay of adc1. the first residue signal is applied to a second conversion stage consisting of a 5-bit adc2, 5-bit dac2, and pipeline th4. the second dac requires 10 bits of precision, which is met by the process with no trim. the input to th5 is a second resi- due signal generated by subtracting the quantized output of dac2 from the first residue signal held by th4. th5 drives a final 6-bit adc3. the digital outputs from adc1, adc2, and adc3 are added together and corrected in the digital error correction logic to generate the final output data. the result is a 14-bit parallel digital cmos-compatible word, coded as two C encode encode 0.1 f t1-4t hsms2812 diodes ad6645 clock source figure 8. crystal clock oscillator, differential encode if a low jitter clock is available, another option is to ac-couple a differential ecl/pecl signal to the encode input pins as shown below. the mc100el16 (or same family) from on-semi offers excellent jitter performance. encode encode ad6645 vt vt 0.1 f 0.1 f ecl/ pecl figure 9. differential ecl for encode driving the analog inputs as with most new high-speed, high dynamic range analog-to- digital converters, the analog input to the ad6645 is differential. differential inputs improve on-chip performance as signals are processed through attenuation and gain stages. most of the improvement is a result of differential analog stages having high rejection of even-order harmonics. there are also benefits at the pcb level. first, differential inputs have high common-mode rejection to stray signals such as ground and power noise. sec- ond, they provide good rejection to common-mode signals such as local oscillator feed-through. the ad6645 analog input voltage range is offset from ground by 2.4 v. each analog input connects through a 500 w resistor to the 2.4 v bias voltage and to the input of a differential buffer (fig- ure 2). the resistor network on the input properly biases the followers for maximum linearity and range. therefore, the analog source driving the ad6645 should be ac-coupled to the input pins. since the differential input impedance of the ad6645 is 1 k w , the analog input power requirement is only C w and rs were set to 25 w , along with a 4:1 impedance ratio transformer, the input would match to a 50 w source with a full-scale drive of 4.8 dbm. series resistors (rs) on the secondary side of the transformer should be used to isolate the transformer from a/d. this will limit the amount of dynamic current from the a/d flowing back into the secondary of the transformer. the 50 w impedance matching can also be incorporated on the secondary side of the transformer as shown in the evaluation board schematic (figure 13). ain ain adt4-1wt ad6645 analog input signal 0.1 f r t r s r s figure 10. transformer-coupled analog input circuit in applications where dc-coupling is required, a differential output op amp such as the ad8138 from analog devices can be used to drive the ad6645 (figure 11). the ad8138 op amp provides single-ended-to-differential conversion, which reduces overall system cost and minimizes layout requirements.
rev. 0 ?15? ad6645 ad6645 ain ain v ref ad8138 v ocm 5v 499 499 499 499 25 25 c f v in c f digital outputs figure 11. dc-coupled analog input circuit power supplies care should be taken when selecting a power source. the use of linear dc supplies with rise-times of <45 ms is highly recom- mended. switching supplies tend to have radiated components that may be received by the ad6645. each of the power supply pins should be decoupled as closely to the package as possible using 0.1 m f chip capacitors. the ad6645 has separate digital and analog power supply pins. the analog supplies are denoted av cc and the digital supply pins are denoted dv cc . although analog and digital supplies may be tied together, best performance is achieved when the supplies are separate. this is because the fast digital output swings can couple switching current back into the analog sup plies. note that av cc must be held within 5% of 5 v. the ad6645 is specified for dv cc = 3.3 v as this is a common supply for digital asics. digital outputs care must be taken when designing the data receivers for the ad 6645. it is recommended that the digital outputs drive a series resistor followed by a gate such as the 74 lcx574. to minim ize capaci- tive loading, there should only be one gate on each output pin. an example of this is shown in the evaluation board schematic shown in figure 13. the digital outputs of the ad6645 have a constant output slew rate of 1 v/ns. a typical cmos gate combined with a pcb trace will have a load of approximately 10 pf. there- fore, as each bit switches 10 ma 10 1 1 pf v ns " () of dynamic current per bit will flow in or out of the device. a full- scale transition can cause up to 140 ma (14 bits 10 ma/bit) of current to flow through the output stages. the series resistors should be placed as close to the ad6645 as possible to limit the amount of current that can flow into the output stage. these switching currents are confined between ground and the dv cc pin. standard ttl gates should be avoided since they can appre- ciably add to the dynamic switching cur rents of the ad6645. it should be noted that extra capacitive loading will increase out- put timing and invalidate timing specifications. digital output timing is guaranteed for output loads up to 10 pf. digital output states for given analog input levels are shown in table i. grounding for optimum performance, it is highly recommended that a com- mon ground be utilized between the analog and digital power planes. the primary concern with splitting grounds is that dynamic currents may be forced to travel significant distances in the sys- tem before recombining back at the common source ground. this can result in a large and undesirable ground loop. the most common place for this to occur is on the digital outputs of the adc. ground loops can contribute to digital noise being coupled back onto the adc front end. this can manifest itself as either harmonic spurs, or very high order spurious products that can cause excessive spikes on the noise floor. this noise coupling is less likely to occur at lower clock speeds since the digital noise has more time to settle between samples. in general, splitting the analog and digital grounds can frequently contribute to undesir- able emi-rfi and should therefore be avoided. conversely, if not properly implemented, common grounding can actually impose additional noise issues since the digital ground currents are riding on top of the analog ground currents in close proximity to the adc input. to minimize the potential for noise coupling further, it is highly recommended that multiple ground return traces/vias be placed such that the digital output currents do not flow back towards the analog front end, but are routed quickly away from the adc. this does not require a split in the ground plane and can be accomplished by simply placing substantial ground connections directly back to the supply at a point between the analog front end and the digital outputs. the judi cious use of ceramic chip capacitors between the power supply and ground planes will also help suppress digital noise. the layout should incorporate enough bulk capacitance to supply the peak current requirements during switching periods. layout information the schematic of the evaluation board (figure 13) represents a typical implementation of the ad6645. a multilayer board is recommended to achieve best results. it is highly recommended that high quality, ceramic chip capacitors be used to decouple each supply pin to ground directly at the device. the pinout of the ad6645 facilitates ease of use in the implementation of high-frequency, high-resolution design practices. all of the digital outputs are segregated to two sides of the chip, with the inputs on the opposite side for isolation purposes. care should be taken when routing the digital output traces. to prevent coupling through the digital outputs into the analog portion of the ad6645, minimal capacitive loading should be placed on these outputs. it is recommended that a fan-out of only one gate should be used for all ad6645 digital outputs. the layout of the encode circuit is equally critical. any noise received on this circuitry will result in corruption in the digitiza- tion process and lower overall performance. the encode clock must be isolated from the digital outputs and the analog inputs. table i. two?s complement output coding ain ain v ref + 0.55 v v ref C 0.55 v positive fs 01 1111 1111 1111 v ref v ref midscale 00 0/11 1 v ref C 0.55 v v ref + 0.55 v negative fs 10 0000 0000 0000
rev. 0 ad6645 ?16? jitter considerations the signal-to-noise ratio (snr) for an adc can be predicted. when normalized to adc codes, the above equation accurately predicts the snr based on three terms. these are jitter, average dnl error, and thermal noise. each of these terms contributes to the noise within the converter. f analog = analog input frequency t j rms = rms jitter of the encode (rms sum of encode source and internal encode circuitry) jitter ? ps 55 00.1 snr ? dbfs 60 65 70 75 80 0.2 0.3 0.4 0.5 0.6 ain = 110mhz ain = 150mhz ain = 190mhz ain = 30mhz ain = 70mhz figure 12. jitter vs. snr snr f t v j rms n n n =- () + + ? ? ? + ? ? ? ? ? 176 20 2 1 2 22 2 2 2 2 1 2 . log p e analog oise rms
rev. 0 ?17? ad6645 table ii. ad6645asq/pcb bill of materials item no. qty reference id 1 description manufacturer 11 6645ee01c ad6644/ad6645 evaluation printed circuit board pcsm, inc. (6645ee01c) 23 c1, c2, c38 capacitor, tantalum smt t491c, 10 m f; 16 v; 10% kemet (t491c106m016as) 39c 3, c7 ? c11, c16, capacitor, smt 0508, 0.1 m f; 16 v; 10% presidio components c30, c32 (0508x7r104k16vp6) 48c 4, c22 ? c26, c29, capacitor, smt 0805, 0.1 m f; 25 v; 10% panasonic (ecj-2vb1e104k) (c33), (c34), c39 50 (c5, c6) capacitor, smt 0805, 0.01 m f; 50 v; 10% panasonic (ecj-2yb1h103k) 69c12 ? c14, c17 ? c21, capacitor, smt 0508, 0.01 m f; 16 v; 10% presidio components c40 (0508x7r103m2p3) 71 cr1 diode, schottky barrier, dual panasonic (ma716-tx) 81 e3, e4, e5 100" straight male header (single row), 3 of 50 pins samtec (tsw-1-50-08-g-s) 94f1 ? f4 emi suppression ferrite chip, smt 0805 steward (hz0805e601r-00) 10 1 j1 connector, pcb pin strip; 5 pins; 5 mm pitch wieland (z5.530.0525.0) 11 1 j1 connector, pcb terminal; 5 pins; 5 mm pitch wieland (25.602.2553.0) 12 1 j2 terminal strip, 50 pin; right angle samtec (tsw-125-08-t-dra) 13 0 (j3) connector, sma; rf; gold johnson components, inc. (142-0701-201) 14 2 j4, j5 connector, coaxial rf receptacle; 50 w amp (227699-2) 15 0 (r1) resistor, smt 0402; 100; 1/16w; 1% panasonic (erj-2rkf1000x) 16 0 (r2) 2 resistor, smt 1206; 60.4; 1/8w; 1% panasonic (erj-8enf60r4v) 17 0 (r3, r4, r5, r8) resistor, smt 0805; 499; 1/10w; 1% panasonic (erj-6enf4990v) 18 2 r6, r7 resistor, smt 0805; 25.5; 1/10w; 1% panasonic (erj-6enf25r5v) 19 1 r9 resistor, smt 0805; 348; 1/10w; 1% panasonic (erj-6enf3480v) 20 1 r10 resistor, smt 0805; 619; 1/10w; 1% panasonic (erj-6enf6190v) 21 0 (r11), (r13) resistor, smt 0805; 66.5; 1/10w; 1% panasonic (erj-6enf66r5v) 22 0 (r12), (r14) resistor, smt 0805; 100; 1/10w; 1% panasonic (erj-6enf1000v) 23 1 r15 2 resistor, smt 0402; 178; 1/16w; 1% panasonic (erj-2rkf1780x) 24 1 r35 resistor, smt 0805; 49.9; 1/10w; 1% panasonic (erj-6enf49r9v) 25 2 rn1, rn3 resistor array, smt 0402; 470; 1/4w; 5% panasonic (exb2hv471jv) 26 2 rn2, rn4 resistor array, smt 0402; 220; 1/4w; 5% panasonic (exb2hv221jv) 27 1 t2 rf transformer, smt kk81, 0.2 ? 350 mhz; 4:1 w ratio mini-circuits (t4-1-kk81) 28 1 t3 rf transformer, smt cd542, 2 ? 775 mhz; 4:1 w ratio mini-circuits (adt4-1wt) 29 1 u1 i.c., qfp-52; 14-bit, 80 msps analog devices (ad6645asq) wideband analog-to-digital converter 30 2 u2, u7 i.c., soic-20; octal d-type flip-flop fairchild (74lcx574wm) 31 0 (u3) i.c., soic-8; low distortion differential adc driver analog devices (ad8138ar) 32 2 u4, u6 i.c., smt sot-23; tinylogic uhs 2-input or gate fairchild (nc7sz32) 33 1 u5 3 clock oscillator, full size mx045; 80 mhz cts reeves (mxo45-80) 34 4 u5 3 connector, miniature spring socket, amp (5-330808-3) 35 0 (u8) i.c., soic-8; differential receiver motorola (mc100el16) 36 4 see drawing circuit board support on base richo (cbsb-14-01) 37 1 see drawing 0.100" shorting block jameco (152670) notes 1 reference designators in parentheses are not installed on standard units. (ac-coupled ain and encode.) ac-coupled ain is standard, r3, r4, r5, r8, and u3 are not installed. if dc-coupled ain is required, c30, t3, and r15 are not installed. ac-coupled encode is standard. c5, c6, c33, c34, r1, r11 ? r14, and u8 are not installed. if pecl encode is required, cr1 and t2 are not installed. 2 r2 is installed for 50 w impedance input matching on the primary of t3. r15 is not installed. r15 is installed for 50 w impedance input matching on the secondary of t3. r2 is not installed. 3 u5 clock oscillator is installed with pin sockets for removal if opt_clk input is used.
rev. 0 ad6645 ?18? 1 2 3 4 5 1 2 3 4 5 6 7 8 9 10 11 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 12 41 42 43 44 45 46 47 48 49 50 51 52 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 rn3 (see note 4) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 u2 gnd clock out en d0 d1 d2 d3 d4 d5 d6 d7 vcc q0 q1 q2 q3 q4 q5 q6 q7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 u7 gnd clock out_en d0 d1 d2 d3 d4 d5 d6 d7 vcc q0 q1 q2 q3 q4 q5 q6 q7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 rn1 (see note 4) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 r2 is installed for input matching on the primary of t3. r15 is not installed. r15 is installed for input matching on the secondary of t3. r2 is not installed. ac-coupled ain is standard. r3, r4, r5, r8, and u3 are not installed. if dc-coupled ain is required, c30, r15, and t3 are not installed. ac-coupled encode is standard. c5, c6, c33, c34, r1, r11?r14 and u8 are not installed. if pecl encode is required, cr1, and t3 are not installed. if ad6644 is used: value for rn1?rn4 is 100 ohm. if ad6645 is used: value for rn1?rn3 is 470 ohm, value for rn2 and rn4 is 220 ohm. notes 1. 2. 3. 4. ad6644/ad6645 gnd vref gnd enc enc gnd avcc avcc gnd ain ain gnd dvcc avcc gnd gnd gnd c1 c2 avcc avcc gnd avcc gnd gnd avcc d3 d2 d1 d0 dmid gnd dvcc ovr avcc dnc gnd avcc gnd dry d13 d12 d11 d10 d9 d8 d7 d6 dvcc gnd d5 d4 dc-coupled ain option 2 1 2 1 2 3 4 5 gnd buflat u6 buflat ferrite 12 f2 + 3p3vin +3p3v j2 +3 p3vd 1 2 3 4 1 2 j1 +3p3 vin ?5v 5 f1 c2 10 f c16 0.1 f c17 0.01 f c18 0.01 f c19 0.01 f c20 0.01 f c21 0.01 f c40 0.01 f c39 0.1 f c38 10 f 12 + 3p3v c1 10 f c9 0.1 f c10 0.1 f c11 0.01 f c12 0.01 f c13 0.01 f c14 0.01 f c23 0.1 f c24 0.1 f c25 0.1 f c26 0.1 f +5va +5va +5va +5va +5va c8 0.1 f c7 0.1 f +5va +5va +3 p3v pref gnd + 3p3v dr_out +3 p3v c32 0.1 f vref +5va +5va rn4 (see note 4) r7 25 r6 25 r15 1 176.4 1 2 3 6 5 4 t3 impedance ratio adt4-1wt 4:1 c30 0.1 f r2 1 60.4 1 2 j5 ain 1 8 3 2 6 4 5 ad8138 r4 499 vref ?5v u3 +5va r5 499 r3 499 r5 499 c29 0.1 f t2 impedance ratio 1:4 3 2 1 4 612 3 cr1 c4 0.1 f 1 2 enc j4 r35 49.9 r13 66.5 r14 100 c34 0.1 f c33 0.1 f r11 66.5 r12 100 +5va +5va 1 2 3 4 8 7 6 5 nc vbb vcc vee u8 +5va c6 0.01 f r1 100 c5 .01 f pecl encode option 3 gnd ferrite +5va c22 0.1 f vcc out nc gnd u5 c3 0.1 f e3 e5 e4 buflat dr_out +3 p3vd u4 r10 619 r9 348 114 78 k1115 66.66mhz (ad6644) 80mhz (ad6645) opt_clk j3 buflat nc7sz32 bnc bnc + 3p3vd +3 p3vd nc7sz32 mc100el16 74lcx574 ferrite ferrite +5va ?5v + + sma +3p3v opt_lat v1 r8 q q d d optional hsms2812 header 50 74lcx574 b06 b07 b08 b09 b10 b11 b12 b13 b00 b01 b02 b03 b04 b05 ovr +3 p3vd f3 f4 rn2 (see note 4) figure 13. evaluation board schematic
rev. 0 ?19? ad6645 figure 14. top signal level figure 15. 5.0 v/3.3 v plane layers 3 and 4 figure 16. ground plane layer 2 and 5 figure 17. bottom signal layer
rev. 0 ?20? c02647?0?2/02(0) printed in u.s.a. ad6645 outline dimensions dimensions shown in millimeters and (inches). 52-lead powerquad 4 (lqfp_ed) (sq-52) 0.65 (0.026) 0.38 (0.015) 0.32 (0.013) 0.22 (0.009) 12.00 (0.472) sq 10.20 (0.402) 10.00 (0.394) sq 9.80 (0.386) top view (pins down) 40 52 1 14 13 26 27 39 7.80 (0.307) 1.60 (0.063) max view a seating plane 0.75 (0.030) 0.60 (0.024) 0.45 (0.018) 0.15 (0.006) 0.05 (0.002) view a 0.10 (0.004) coplanarity 1.45 (0.057) 1.40 (0.055) 1.35 (0.053) 40 52 1 14 13 26 27 39 exposed heatsink (centered) 2.35 (0.093) 2.20 (0.087) 2.05 (0.081) (4 plcs) 6.00 (0.236) 5.90 (0.232) 5.80 (0.228) 6.00 (0.236) 5.90 (0.232) 5.80 (0.228) 2.65 (0.104) 2.50 (0.098) 2.35 (0.093) (4 plcs) bottom view (pins up) controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. the ad6645 powerquad 4 (lqfp_ed) has a thermally and electrically conductive heat slug exposed on the bottom of the package which can be utilized for enhanced thermal management. it is recommended that no unmasked active pcb traces or vias be located under the package that could come into contact with the grounded heat slug. although not a requirement for specified operation, soldering the slug to a ground plane with sufficient thermal capacity will reduce the junction temperature of the device. this may prove beneficial in high reliability applications where lower junction temperatures typically contribute to increased semiconductor reliability.

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